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| digital signal processor S5L9291X 1 introduction S5L9291X is a signal processing lsi for the cd. digital processing functions (efm demodulation, error correction), spindle motor servo processing, compression for anti-rolling and anti-shock, expandable memory control functions (4m, 16m, 64m edo/fast page dram and 16m, 32m, 64m, 128m, 256m sdram ), 10-band eq (equalizer) filter, cd-text and 1-bit dac for the cd-mp3 interface are installed in S5L9291X. features signal processing part ? efm data demodulation ? frame sync detection, protection, insertion ? sub code data processing (q data crc check, q data register installed) ? error correction (c1: 2 error correction, c2: 4 erasure correction) ? installed 16k sram for de-interleave ? interpolation ? digit al audio interface ? clv/pseudo-cav servo control ? wide capture range digital pll ( 50%) ? cd-text ? variable speed clv control ( 1 to 2 ) ? cd mp3 interface digital filter, dac part ? 4 times over sampling digital filter ? digital de-emphasis ? 10 band eq function ? sigma-delta stereo dac installed ? audio l.p.f installed memory control part ? 4/5/6 bit compression and expandable control ? full bit control ? 4m/16m/64m, 4, 8, 16 edo/ fastpage dram support ? 16m/64m/128m/2 56m, 32m(16m 2ea), 8, 16 sdram support ordering information device package supply voltage operating temperature S5L9291X01-t0r0 100-tqfp-1414 2.7 to 3.3v -20 to +75 c 100-tqfp-1414
S5L9291X digital signal processor 2 block diagram dpll clv servo lock smef smon smdp smds wdck testv lock smef smon smdp smds wdck efmi vco1lp vco2lp timing generator micom interface wfck rfck c4m xin istat mlt mdat mck mute subcode out efm demodulator ecc 16k sram address generator sqck sbck sos1 sqdt sbdt interpolator i/o interface encoder decoder dram interface jitb lpf pwm ad9 - ad0 d3 - d0 cas1 - cas0 ras we lchout rchout vhalf vref 1-bit dac digital out digital filter c2po datx digital signal processor S5L9291X 3 pin configuration S5L9291X (cddsp+esp) vddd4 c2po vssd3 mnt0 mnt5 mnt4 mnt3 mnt1 mnt2 rfck d15 d14 d13 d12 d11 d10 d9 d8 clk ad12 ad11 ad9 ad8 ad7 ad6 mute vdda_dac vssa_dac vssd_dac vddd_dac sqck sqdt lchout vref mdat mck istat s0s1 vhalf rchout sbdt sbck c4m test3 test1 test2 vssd2 jitb datx vddd3 1 vdda_pll vssa_pll vddd_pll vssd_pll vco1lf vco2lf vddd1 efmi lock smef smdp smds vssd1 wdck xout xin test0 pbck smon lkfs resetb mlt wfck vddd2 testv ad1 ad0 ad10 ba1 (cs1) ba0 cs0 ras cas d7 d6 d5 d4 d3 vssd4 ad2 ad5 ad4 ad3 d2 vddd6 d1 d0 we vddd5 vssd5 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 S5L9291X digital signal processor 4 pin description pin no symbol i/o description 1 vdda_pll - analog power for dpll 2 vssa_pll - analog ground for dpll 3 vco1lf o pump out for vco1 4 vco2lf o pump out for vco2 5 vssd_pll - digital ground separated bulk bias for dpll 6 vddd_pll - digital power separated bulk bias for dpll 7 pbck o vco1/2 clock output (4.3218mhz) 8 vddd1 - digital power 9 xin i x'tal oscillator input (16.9344mhz) 10 xout o x'tal oscillator output 11 vssd1 - digital ground 12 test0 i test input 13 efmi i efm signal input 14 lock o clv servo locking status output 15 smef o lpf time constant control of the spindle servo error signal 16 smon o on/off control signal for spindle servo 17 smdp o phase control output for spindle motor drive 18 smds o speed control output for spindle motor drive 19 wdck o word clock output ( 1: 88.2khz, 2: 176.4khz) 20 vddd2 - digital power 21 testv i various test input 22 wfck o write base clock output 23 lkfs o the lock status output of frame sync 24 resetb i system reset at "l" 25 mlt i latch signal input from micom 26 mdat i serial data input from micom 27 mck i serial data receiving clock input from micom 28 istat o the internal status output to micom (3-state output) 29 s0s1 i/o subcode sync signal (s0+s1) output 30 sqck i subcode-q data transferring bit clock input 31 sqdt o subcode-q data serial output 32 vddd3 - digital power 33 vssd2 - digital ground digital signal processor S5L9291X 5 pin description ( continued) pin no symbol i/o description 34 sbck i subcode data transferring bit clock 35 sbdt i/o subcode data serial output 36 mute i system mute at "h" 37 c4m o 4.2336mhz clock output 38 test1 i test input 39 test2 i test input 40 lchout o left-channel audio output through dac 41 vdda_dac - analog power for dac 42 vhalf o reference voltage output for bypass 43 vref o reference voltage output for bypass 44 vssa_dac - analog ground for dac 45 rchout o right-channel audio output through dac 46 vddd_dac - digital power for dac 47 vssd_dac - digital ground for dac 48 test3 i test input 49 datx o digital audio data output 50 jitb i/o internal sram jitter margin status output 51 c2po o c2 pointer output 52 rfck i/o read base clock output 53 mnt0 i/o monitoring signal output 54 mnt1 i/o monitoring signal output 55 mnt2 i/o monitoring signal output 56 mnt3 i/o monitoring signal output 57 mnt4 i/o monitoring signal output 58 mnt5 i/o monitoring signal output 59 vssd3 - digital ground 60 vddd4 - digital power 61 d15 i/o dram data input/output 15 (3-state output) 62 d14 i/o dram data input/output 14 (3-state output) 63 d13 i/o dram data input/output 13 (3-state output) 64 d12 i/o dram data input/output 12 (3-state output) 65 d11 i/o dram data input/output 11 (3-state output) 66 d10 i/o dram data input/output 10 (3-state output) 67 d9 i/o dram data input/output 9 (3-state output) S5L9291X digital signal processor 6 pin description ( continued) pin no symbol i/o description 68 d8 i/o dram data input/output 8 (3-state output) 69 clk o sdram clock(4mhz) (3-state output 70 ad12 o dram address output 12 (3-state output) 71 ad11 o dram address output 11 (3-state output) 72 ad9 o dram address output 9 (3-state output) 73 ad8 o dram address output 8 (3-state output) 74 ad7 o dram address output 7 (3-state output) 75 ad6 o dram address output 6 (3-state output) 76 ad5 o dram address output 5 (3-state output) 77 ad4 o dram address output 4 (3-state output) 78 ad3 o dram address output 3 (3-state output) 79 vssd4 - digital ground 80 vddd5 - digital power 81 ad2 o dram address output 2 (3-state output) 82 ad1 o dram address output 1 (3-state output) 83 ad0 o dram address output 0 (3-state output) 84 ad10 o dram address output 10 (3-state output) 85 ba1(cs1) o bank address 1 / dram chip select 1 (3-state output) 86 ba0 o bank address 0 (3-state output) 87 cs0 o dram chip select 0 (3-state output) 88 ras o dram row address selection output (active low) (3-state output) 89 cas o dram column address selection output 0 (active low) (3-state output) 90 we o dram write enable output (active low) (3-state output) 91 vssd5 - digital ground 92 vddd6 - digital power 93 d7 i/o dram data input/output 7 (3-state output) 94 d6 i/o dram data input/output 6 (3-state output) 95 d5 i/o dram data input/output 5 (3-state output) 96 d4 i/o dram data input/output 4 (3-state output) 97 d3 i/o dram data input/output 3 (3-state output) 98 d2 i/o dram data input/output 2 (3-state output) 99 d1 i/o dram data input/output 1 (3-state output) 100 d0 i/o dram data input/output 0 (3-state output) digital signal processor S5L9291X 7 maximum absolute ratings item symbol rating unit power supply voltage v dd -0.3 to 3.8 v input supply voltage v i -0.3 to v dd + 0.3 v operating temperature t opr -20 to 75 c storage temperature t stg -40 to 125 c electrical characteristics operating condition item symbol operating range unit power supply voltage v dd 2.7 to 3.3 v operating temp. t opr -20 to 75 c S5L9291X digital signal processor 8 dc characteristic (v dd = 3.0v, v ss = 0v, ta = 25 c) item symbol condition design values unit comment min typ max 'h' input voltage1 v ih 0.8v dd - - v (note 1) 'l' input voltage1 v il - - 0.2v dd v 'h' output voltage1 v oh(1) i oh = -1ma 2.4 - - v (note 2) 'l' output voltage1 v ol(1) i ol = 1ma - - 0.4 v 'h' output voltage2 v oh(2) i oh = -1ma 2.4 - - v (note 3) 'l' output voltage2 v ol(2) i ol = 1ma - - 0.4 v 'h' output voltage3 v oh(3) i oh = -1ma 2.4 - - v (note 4) 'l' output voltage3 v ol(3) i ol = 1ma - - 0.4 v input leak current1 i lkg1 v i = 0-v dd -10 - 10 ua (note 5) input leak current2 i lkg2 v i = 0-v dd -10 - 10 ua (note 6) three state output leak current i o(lkg) v o = 0-v dd -10 - 10 ua (note 7) notes: 1. related pins: all input, bi-direction terminal (input mode) 2. related pins: all output terminal 3. related pins: all bi-direction terminal (output mode) 4. related pins: all tri-state output terminal 5. related pins: all input terminal (excluding xin ) 6. related pins: xin 7. related pins: smef, smdp, smds, istat digital signal processor S5L9291X 9 ac characteristic when pulse is applied to x in ( ta = 25 c, v dd = 3.0v, v ss = 0v) item symbol min typ max unit 'h' level pulse width t wh 13 - - ns 'l' level pulse width t wl 13 - - ns pulse frequency t ck 26 - - ns input 'h' level v ih v dd -1.0 - - v input 'l' level v il - - 0.8 v rising & falling time t r ,t f - - 10 ns v ih _max*0.9 v il _max*0.1 v il _min t r t f t wh t wl tck v ih _max v dd /2 S5L9291X digital signal processor 10 mck, mdat, mlt, sqck ( ta = 25 c, v dd = 3.0v, v ss = 0v) item symbol max typ min unit clock frequency f ck1 1 - - mhz clock pule width t wck1 - - 500 ns setup time t su - - 300 ns hold time t h - - 300 ns delay time t d - - 300 ns latch pulse width t w - - 1000 ns sqck frequency f ck2 1 - - mhz sqck pulse width t wck2 - - 500 ns t wck1 t wck1 1/f ck 1 t su t h t d t w t wck2 t wck2 1/f ck2 t su t h sqdt sqck mlt mdat mck digital signal processor S5L9291X 11 edo-dram, fast-page dram interface timing read cycle data-out column address row address 2t 1t 1t 4t 4t 2t 1t 1t ras cas addr we data[3:0] don't care oe = gnd 2t 1t = 59ns/2 at bus x4 1t = 59ns at bus x8, x16 write cycle data-in column address row address 2t 1t 1t 4t 4t 2t 2t 2t ras cas addr we data[3:0] don't care oe = gnd 1t = 59ns/2 at bus x4 1t = 59ns at bus x8, x16 2t S5L9291X digital signal processor 12 cas-before-ras refresh cycle 2t ras cas 2t 1t = 59ns/2 at bus x4 1t = 59ns at bus x8, x16 digital signal processor S5L9291X 13 sdram interface timing read (with auto precharge) cycle 4t data-out row address column address 4t 2t ras cas addr a0-a9,a11 we data[3:0] cas latency 2 1t=59ns at bus x8,x16 2t don't care cs = gnd cke = vdd dqm = gnd clk row address a10 enable auto precharge bank bank ba0,ba1 2t S5L9291X digital signal processor 14 write (with auto precharge) cycle cas latency 2 1t=59ns at bus x8,x16 don't care cs = gnd cke = vdd dqm = gnd data-out row address column address 4t 2t ras cas addr we data[3:0] 2t 2t clk row address a10 enable auto precharge bank bank ba0,ba1 auto refresh cycle cas latency 2 1t=59ns at bus x8,x16 don't care cs = gnd we = vdd cke = vdd ras 2t 2t clk cas digital signal processor S5L9291X 15 description of operation micom interface each command is executed when data and command is input as lsb first according to timing shown in the figure below through mdat, mck, and mlt inputs and istat output. read/write mode support address: 8-bit data: 8-bit (writing), 8/16-bit (reading) d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 [msb] valid mdat mck mlt register (write cycle) d8 d9 d10 d11 d12 d13 d14 d15 [msb] mdat mck mlt istat (read cycle-1: $b5, $b6) s7 s6 s5 s2 s1 s0 ... d8 d9 d10 d11 d12 d13 d14 d15 [msb] mdat mck mlt istat (read cycle-2: $b7) r15 r14 r13 r12-r3 r2 r1 r0 ... s4 s3 S5L9291X digital signal processor 16 dsp command command address data istat d7 d6 d5 d4 d3 d2 d1 d0 terminal dac attn control 01011101 ($5d) m5 m4 m3 m2 m1 mo soft attn c md direct hi-z dpll control 1 10001000 ($88) wide inc3t phase gain dlf gain acc 3t co1t co2t retref hi-z dpll control 2 10001001 ($89) ref98[1:0] ref[1:0] maxtgain[1:0] caprange[1:0] hi-z dpll control 3 10001010 ($8a) divs1[1:0] divp1[5:0] hi-z dpll control 4 10001011 ($8b) divs2[1:0] divp2[5:0] hi-z dpll control 5 10001100 ($8c) divm2[7:0] hi-z dpll control 6 10001101 ($8d) c md split phase only mrange[1:0] fsreg pll test pll pwrdn1 pll pwrdn2 hi-z function control 10010000 ($90) cdrom fdeem deem era off c1pnt c1pnt sw - jitm hi-z audio control 10010001 ($91) mute zcmt zdenl attn dac mute v flag datx mute datx oen s0s1 frame sync control 10010010 ($92) fsel[1:0] wsel[1:0] fsmd[1:0] scs[1:0] lkfs mode control 1 10010011 ($93) cddsp pwdn esp pwdn eq pwdn dac pwdnb eclv eclv pd nclv crcq hi-z mode control 2 10010100 ($94) msck sw dacck sw clvck sw datck sw rfck sw c4m sw jtfrv2 jtfrv1 hi-z cd text 10010101 ($95) geq sw geq2 sw - - - - text on text out hi-z clv gain control 10011000 ($98) ovspl wbn wpn lock high ovspl ms wb wp gain hi-z clv mode control 10011001 ($99) un lock [1:0] clv idle pcen cm[3:0] /(pw 3 64) clv control 1 10011010 ($9a) strio smm pme sme pcksel[1:0] pgain[1:0] hi-z clv control 2 10011011 ($9b) lc pml sml[1:0] pos sgain[2:0] hi-z clv control 3 10011100 ($9c) poffset[7:0] hi-z clv control 4 10011101 ($9d) splus sdd phasediv[1:0] smoffset[3:0] hi-z clv control 5 10011110 ($9e) soffset[7:0] hi-z digital signal processor S5L9291X 17 dsp command (continued) command address data istat d7 d6 d5 d4 d3 d2 d1 d0 terminal clv control 6 10011111 ($9f) - - - - - - - clv dfct hi-z 10band eq. filter gain level(31hz) 10100000 ($a0) - - - eqgb0[4:0] hi-z 10band eq. filter gain level(62hz) 10100001 ($a1) - - - eqgb1[4:0] hi-z 10band eq. filter gain level(125hz) 10100010 ($a2) - - - eqgb2[4:0] hi-z 10band eq. filter gain level(250hz) 10100011 ($a3) - - - eqgb3[4:0] hi-z 10band eq. filter gain level(500hz) 10100100 ($a4) - - - eqgb4[4:0] hi-z 10band eq. filter gain level(1khz) 10100101 ($a5) - - - eqgb5[4:0] hi-z 10band eq. filter gain level(2khz) 10100110 ($a6) - - - eqgb6[4:0] hi-z 10band eq. filter gain level(4khz) 10100111 ($a7) - - - eqgb7[4:0] hi-z 10band eq. filter gain level(8khz) 10101000 ($a8) - - - eqgb8[4:0] hi-z 10band eq. filter gain level(16khz) 10101001 ($a9) - - - eqgb9[4:0] hi-z 10eq volume gain control 10101010 ($aa) eqrst eqon volon eqvg[4:0] hi-z datx & 1-bit dac control 10101110 a3 ? ($ae) - - - - sc[1:0] sf[1:0] hi-z output port control 1 10101111 a9 ? ($af) - talk[2:0] mnt hiz - rfck oen sbdt dumb hi-z play mode control 11110000 ($f0) ds1 ds0 - - play sw dfck play1 play0 hi-z S5L9291X digital signal processor 18 esp write command command address data istat d7 d6 d5 d4 d3 d2 d1 d0 terminal ms control 10110000 ($b0) mswren mswac l msrde n msracl msdcn2 msdcn1 waqv mson hi-z data control 1 10110001 ($b1) dram sel [1:0] yflgs yfckp cmp12 dc comp [1:0] hi-z data control 2 10110010 ($b2) bbw (0) wff (0) mcp (1) esp reset jitb off shock en shock sw cmd shock hi-z data control 3 10110011 ($b3) sbcen - - sbc[4:0] hi-z data control 4 1011_0100 ($b4) dram ctrl ram type ram bank ram_bus[1:0] ram_size[2:0] hi-z esp read command -i command address data s7 s6 s5 s4 s3 s2 s1 s0 ms state 1 10110101 ($b5) flag6 msovfl dcomp mswi h msrih ms state 2 10110110 ($b6) msemp ovfl encod decod esp read command - ii command address data r[15:0] ms data residual 10110111 ($b7) am[21:6] digital signal processor S5L9291X 19 micom dram write command command address data istat d1 d2 d3 d4 d5 d6 d7 d8 terminal dram access 0 10111010 ($ba) mwr mrd - - mad[11:8] hi-z dram access 1 10111011 ($bb) mad[7:0] hi-z dram access 2 10111100 ($bc) wrdata[15:8] hi-z dram access 3 10111101 ($bd) wrdata[7:0] hi-z micom dram read command command address data d1 d2 d3 d4 d5 d6 d7 d8 dram access read data 10111111 ($bf) rddata[15:0] S5L9291X digital signal processor 20 $5d command digital attenuation level control command address data d7 d6 d5 d4 d3 d2 d1 d0 dac attn control 01011101 ($5d) m5 m4 m3 m2 m1 m0 soft attn cmd direct mdat attenuation level (db) mdat attenuation level (db) msb lsb m5 m4 m3 m2 m1 m0 msb lsb m5 m4 m3 m2 m1 m0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 -0.28 -0.42 -0.56 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 -6.30 -6.58 -6.88 -7.18 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 -0.71 -0.86 -1.01 -1.16 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 -7.50 -7.82 -8.16 -8.52 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 -1.32 -1.48 -1.64 -1.80 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 -8.89 -9.28 -9.68 -10.10 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 -1.97 -2.14 -2.32 -2.50 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 -10.55 -11.02 -11.51 -12.04 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 -2.68 -2.87 -3.06 -3.25 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 -12.60 -13.20 -13.84 -14.54 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 -3.45 -3.66 -3.87 -4.08 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 -15.30 -16.12 -17.04 -18.06 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 -4.30 -4.53 -4.76 -5.00 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 -19.22 -20.56 -22.14 -24.08 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 -5.24 -5.49 -5.75 -6.02 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 -26.58 -30.10 -36.12 - digital signal processor S5L9291X 21 soft attn enable soft attenuation. the attenuation level is divided into 64 steps. 0 db - db soft attn set1 set2 set3 set4 set5 set6 smoothly directly 23.2ms < soft attenuation operation > 8 ? cmd direct (option) l : attenuate th e 1-bit dac using the soft attenuation block. h : apply direct attenuation level to the 1-bit dac without using the soft attenuation block. this disables the soft attenuation. S5L9291X digital signal processor 22 $88 command (default values d[7:0] = 0000 0000) digital pll control command address data d7 d6 d5 d4 d3 d2 d1 d0 dpll control 1 10001000 ($88) wide inc3t phase gain dlf gain acc3t co1t co2t retref bit name data = 0 data = 1 comment d7 wide normal wide wide mode select d6 inc3t normal new 3t frequency error application d5 phase_gain 1/2t 1t phase adjust selection (option) d4 dlf_gain 1/2^10 1/2^9 digital loop filter gain selection d3 acc3t ignore 3t accept 3t rom coefficient selection d2 co1t normal 1t correction 1t ? 3t correction d1 co2t normal 2t correction 2t ? 3t correction d0 retref 1.1% 2.3% reference when return to m1 = 98 $89 command (default value d [7:0] = 1111 0000) digital pll control command address data d7 d6 d5 d4 d3 d2 d1 d0 dpll control 2 10001001 ($89) ref98[1:0] ref[1:0] maxtgain[1:0] caprange[1:0] bits name data = 00 data = 01 data = 10 data = 11 comment d[7:6] ref98[1:0] 1.7% 2.3% 3.4% 4.6% outward reference when m1 = 98 d[5:4] ref[1:0] 1.7% 2.3% 3.4% 4.6% outward reference when m1 1 98 d[3:2] maxtgain[1:0] 1 1/2 1/4 1/8 max t accumulation gain d[1:0] caprange[1:0] 50% 40% 30% 20% capture range selection digital signal processor S5L9291X 23 $8a command (default values d [7:0] = 0101 0110) digital pll control command address data d7 d6 d5 d4 d3 d2 d1 d0 dpll control 3 10001010 ($8a) divs1[1:0] divp1[5:0] bits name data = 00 data = 01 data = 10 data = 11 comment d[7:6] divs1[1:0] 1 1/2 1/4 1/8 pll1 post scaler bits name data = 000000 - 111111 comment d[5:0] divp1[5:0] 0 - 63 pll1 pre divider $8b command (default value d [7:0] = 1001 0110) digital pll control command address data d7 d6 d5 d4 d3 d2 d1 d0 dpll control 4 10001011 ($8b) divs2[1:0] divp2[5:0] bits name data = 00 data = 01 data = 10 data = 11 comment d[7:6] divs2[1:0] 1 1/2 1/4 1/8 pll2 post scalar bits name data = 000000 - 111111 comment d[5:0] divp2[5:0] 0 - 63 pll2 pre divider $8c command (default values d [7:0] = 0101 0000) digital pll control command address data d7 d6 d5 d4 d3 d2 d1 d0 dpll control 5 10001100 ($8c) divm2[7:0] bits name data = 00000000 - 11111111 comment d[7:0] divm2[7:0] 0 - 255 pll2 main divider S5L9291X digital signal processor 24 $8d command (default values d [7:0] = 0000 0000) digital pll control command address data d7 d6 d5 d4 d3 d2 d1 d0 dpll control 6 10001101 ($8d) cmd split phase only mrange[1:0] fsreg pll test pll pwrdn1 pll pwrdn2 cmd_split (option) the digital pll control micom command is automatically applied when the speed is changed($f0) or at jitter free2($94). h : each dpll control micom commands ($8a, $8b, $8b) are applied using the micom interface terminals (mck, mdat, mlt). l : dpll control micom command ($8a, $8b, $8b) is applied automatically inside. phase_only (option) controls phase compensation status at dpll. h : phase compensation l : phase compensation + frequency compensation mrange[1:0] controls the range of the pl l1 main divider m value range bits name data = 00 data = 01 data = 10 data = 11 comment d[5:4] mrange[1:0] 50% 40% 30% 20% lock range fsreg verifies the frame sync status(|thigh- tlow| 1) at max t h : verify l : ignore plltest pll1 test mode h : test (m1<=m2), l : normal pll pwdn1 pll1 power down mode h : power down, l : normal pll pwdn2 pll2 power down mode h : power down, l : normal digital signal processor S5L9291X 25 $90 command dsp function control (default values d [7:0] = 0000 0000) dsp function control command address data d7 d6 d5 d4 d3 d2 d1 d0 function control 10010000 ($90) cdrom fdeem deem era off c1pnt c1pnt sw - jitm cdrom h: cdrom mode (interpolation off) l: cdp mode (interpolation on) fdeem, deem de-emphasis automatic control and compulsion control select fdeem deem de-emphasis on/off comment 0 0 off - 0 1 on/off automatic operate to detect emphasis signal of subcode information 1 0 off - 1 1 on operate without regard to emphasis signal of subcode information era_off: h: erasure corr ection off l: erasure correction on c1pnt : c1 2 error correction c1 pointer set/reset control h: c1pnt = reset l: c1pnt = set c1pnt_sw: c1pnt set/reset command input method control h: testv terminal use l: micom command use c1pnt (option) mute sram address copy permission (write base count copy from read base counter) h: accept l: reject S5L9291X digital signal processor 26 $91 command (default values d [7:0] = 1000 1000) control of each function related to audio data command address data d7 d6 d5 d4 d3 d2 d1 d0 audio control 10010001 ($91) mute zcmt zdenl attn dac mute vfalg datx mute datx oen mute dsp mute enable signal h : dsp mute on l : dsp mute off zcmt dsp zero cross mute enable signal (valid when mute on) h : dsp zero cross mute on, l : dsp zero cross mute off zdenl zero detection mute disable h : disable l : enable attn dsp attenuation control h : dsp attenuation on l : dsp attenuation off dac mute sets 1-bit dac block input data to 'l'. h : dac mute on, l : dac mute off vfalg datx block input v-bit control h : set to 'l' l : c2po datx_mute sets digital audio interface block input data to 'l'. h : datx mute on l : datx mute off datx_oen datx output function enable. h : enable l : disable digital signal processor S5L9291X 27 $92 command (default values d [7:0] = 0000 0000 ) control of functions related to frame sync command address data d7 d6 d5 d4 d3 d2 d1 d0 frame sync control 10010010 ($92) fsel[1:0] wsel[1:0] fsmd[1:0] scs[1:0] fsel[1:0]: control of cycle for frame sync protection and insertion fsel[1:0] control cycle (frame) 00 2 01 4 10 8 11 13 wsel[1:0]: control of window size related to frame sync protection wsel[1:0] window size(t) 00 3 01 7 10 13 11 26 fsmd: [1:0] frame sync detection method control fsmd [1:0] detection method comment 00 pattern 11t ? 11t 01 compensation 11t ? 11t, 10 ? 12t, 12t ? 10t 10 cycle 1 10t ? 11t, 11t ? 12t, 11t ? 11t, 11t ? 10t, 12t ? 11t 11 cycle 2 cycle 1, 10t ? 12t, 12t ? 10t scs[1:0] subcode sync s0s1 select scs[1:0] s0s1 (pad or esp) sqok sync (to subcode) 00 s0 or s1 s0 or s1 01 windowed s0 or s1 s0 or s1 10 windowed s0 and s1 s0 and s1 11 windowed s0 and s1 windowed s0 and s1 S5L9291X digital signal processor 28 $93 command (default values d [7:0] = 0010 0001) control of modes of functions in dsp command address data d7 d6 d5 d4 d3 d2 d1 d0 mode control 1 10010011 ($93) cddsp pwdn esp pwrdn eq pwdn dac pwdnb eclv eclv pd nclv crcq cddsp_pwdn cddsp function power down h : power down, l : power down off esp_pwdn esp function power down h : power d own on, l : power down off eq_pwdn eq(equalizer) function power down h : power down, l : power down off dac_pwdnb 1-bit dac function power down h : power down off, l : power down eclv emergency clv servo, overflow prevention h : repeat output of h, hi-z, and l at a regular cycle through the smdp terminal l : normal operation eclv_pd smdp output cycle control at eclv h: bottom hold cycle (refer to $98) l : peak hold cycle (refer to $98 ) nclv h : clv phase servo driv en by frame sync l : clv phase servo driven by base counter crcq l : sqdt without sqok h : sqdt with sqok (if s0s1 is 'h', sqdt = sqok) digital signal processor S5L9291X 29 $94 command (default values d [7:0] = 0000 0000 ) control of function modes in dsp command address data d7 d6 d5 d4 d3 d2 d1 d0 mode control 2 10010100 ($94) msck sw dacck, sw clvck sw datck sw rfck sw c4m sw jtfrv2 jtfrv1 bit value 1-bit dac master clock {d7,d6} 1x input to rfck terminal for external clock source $a9 d1(rfck_oen) is always "l". 01 vco2(pll block clock) 00 x'tal bit name data = 0 data = 1 comment d5 clvck_sw x'tal vco2 fixed x'tal or variable x'tal conversion d4 datck_sw x'tal vco2 fixed x'tal or variable x'tal conversion d3 rfck_sw x'tal/vco x'tal use rfck clock in clv servo processing according to jitter free mode d2 c4m_sw x'tal vco2 fixed x'tal or variable x'tal conversion d1 jtfrv2 x'tal vco2 use the variable vco2 clock in data processing according to vco1 d0 jtfrv1 x'tal vco1 use vco1 clock in data processing S5L9291X digital signal processor 30 $95 command (default values d[7:0] = 0000 0000) control of cd text mode command address data d7 d6 d5 d4 d3 d2 d1 d0 cd text 10010101 ($95) geq sw geq2 sw - - - - text on text out geq_sw,geq2_sw bit value geq master clock dacck_sw == 0 dacck_sw == 1 {d7,d6} 00 xi*2/3(11mhz) vco2*2/3 10 xi(16.9344mhz) x1 input to rfck terminal for external clock source $a9 d1(rfck_oen) is always "l" geq power optimization command value cddsp external audio source(ex:mp3) sampling frequency 44.1khz 32khz 44.1khz 48khz $94 {d7,d6} 00 10 00 10 $95 {d7,d6} 00 01 00 10 texton cd text function on/off signal. h : cd text function enable, l : cd text function disable textout cd text information output control on/off signal h : sqdt with signal cd-text information transmission enable, l : disable digital signal processor S5L9291X 31 $98 command (default values d [7:0] = 0000 0111) control cycle and gain control in clv speed mode command address data d7 d6 d5 d4 d3 d2 d1 d0 clv gain control 10011000 ($98) ovspl wbn wpn lock high ovspl ms wb wp gain ovspl (option) over sampling of clv output (smdp, smds) cycle by 7.35khz * 4 and output. h : over-sampling enable l : over-sampling disable wbn (option) clv speed mode bottom hold cycle control h : rfck/64 l : determined by wb wpn (option) clv speed mode peak hold cycle control h : rfck/8 l : determined by wp lock_high lock pad as 'h' while command is input. h : lock high l : normal lock ovspl_ms (option) over-sampling enable smds output mode select h : pwm (h, l) l : tri-state (h, hi-z, l) wb clv speed mode bottom hold cycle control h : rfck/16 l : rfck/32 wp clv speed mode peak hold cycle control h : rfck/2 l : rfck/4 {wpn,wp} control cycle {wbn,wb} control cycle 00 rfck/4 00 rfck/32 01 rfck/2 01 rfck/16 10 rfck/8 10 rfck/64 11 1rfck/8 11 rfck/64 gain clv speed mode smds output gain control h : 0db l : -12db S5L9291X digital signal processor 32 $99 command (default values d [7:0] = 0000 0000 ) clv mode control command address data d7 d6 d5 d4 d3 d2 d1 d0 clv mode control 10011001 ($99) unlock [1:0] clv idle pcen cm[3:0] unlock[1:0] unlock cycle control unlock[1:0] function 00 if lkfs can remain at 'l' for 128 frames, the lock is 'l'. 01 if lkfs can remain at 'l' for 96 frames, the lock is 'l'. 10 if lkfs can remain at 'l' for 192 frames, the lock is 'l'. 11 if lkfs can remain at 'l' for 224 frames, the lock is 'l'. clv_idle use to place clv servo control in idle mode. (set pos ($9b) to 'h') h : output a specific error ($9e, soffset[7:0])to the smds terminal, idle mode . l : normal mode pcen phase error masking status determination when setting the dead zone. h : smdp phase error masking enable. (when wfck frequency error has entered the dead zone) l : smdp phase error masking disable. cm[3:0] clv servo control mode setting mode cm[3:0] smdp smds smef smon function forward (kick) 1 0 0 0 h hi-z l h spindle motor forward mode reverse (brake) 1 0 1 0 l hi-z l h spindle motor reverse mode high speed (clv-h) 1 1 0 0 speed hi-z l h rough servo mode at jump speed (clv-s) 1 1 1 0 speed hi-z l h rough servo mode at start up phase (clv-p) 1 1 1 1 phase phase hi-z h pll servo mode xphsp (clv-a) 0 1 1 0 speed phase hi-z phase l hi-z h normal play mode (when lock is 'h', clv-p operation and when 'l', clv-s operation ) vphsp (clv-a) 0 1 0 1 speed phase hi-z phase l hi-z h automatic servo mode (when lock is 'h' or gfs is 'h', operate in clv-p, but others, operate in clv-s') stop (stop) 0 0 0 0 l hi-z l l spindle motor stop mode digital signal processor S5L9291X 33 $9a command (default values d [7:0] = 0000 0000) digital clv control command address data d7 d6 d5 d4 d3 d2 d1 d0 clv control 1 10011010 ($9a) strio smm pme sme pcksel[1:0] pgain[1:0] strio: tri-state out enable in phase mode h: tri-state l: pwm smm: smds mask limit manual setting enable h: manual setting l: auto setting pme: smdp mask enable h: mask enable l: mask disable sme smds mask enable (dead zone enable) h: mask enable l: mask disable pcksel[1:0]: mdp resolution clock selection bits name data = 00 data = 01 data = 10 data = 11 comment d[3:2] pcksel [1:0] clk4m_ clv/2 clk4m_ clv/4 clk4m_ clv/8 clk4m_ clv/16 mdp resolution clock selection pgain: smdp gain setting bits name data = 00 data = 01 data = 10 data = 11 comment d[1:0] pgain[1:0] 1 1/2 1/4 1/8 mdp gain selection S5L9291X digital signal processor 34 $9b command (default values [7:0] = 0000 0010) digital clv control command address data d7 d6 d5 d4 d3 d2 d1 d0 clv control 2 10011011 ($9b) lc pml sml[1:0] pos sgain[2:0] lc: lock control h : 1x ? 2x or 2x ? 1x then lock is forced to 0 l : normal lock control pml : smdp mask limit h : smdp mask for smds error center value 50% l : smdp mask for smds error center value 25% sml: mds mask limit (dead zone area) at mds error center value bits name data = 00 data = 01 data = 10 data = 11 comment d[5:4] sml[1:0] 0% 6.25% 12.5% 25% dead zone selection when it enters the dead zone around the data rate, the mds error value is output as 0. this minimizes the change in plus(+) and minus(-) frequently generated in the reference data rate and reduces the number of times required for motor control to reduce power consumption. the phase control also turns off in this dead zone. pos: mdp output selection h: gain controlled smdp l: normal smdp sgain: smds gain setting sgain[2:0] gain value 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 digital signal processor S5L9291X 35 $9c command (default values d [7:0] = 0000 0000) digital clv control command address data d7 d6 d5 d4 d3 d2 d1 d0 clv control 3 10011100 ($9c) poffset[7:0] poffset[7]:smdp offset sign h: minus (-) l: plus (+) poffset[6:0]: smdp offset absolute value $9d command (default values d [7:0] = 0000 0000 ) digital clv control command address data d7 d6 d5 d4 d3 d2 d1 d0 clv control 4 10011101 ($9d) splus sdd phasediv[1:0] smoffset[3:0] splus: smds offset plus enable h: enable l: disable sdd: smds speed down control disable h: speed down control disable l: speed down control enable phasediv[5:4]: phase comparator period setting bits name data = 00 data = 01 data = 10 data = 11 comment d[5:4] phasediv [1:0] rfck/2 rfck/4 rfck/8 rfck/16 phase comparator period selection smoffset[3:0]:smds mask limit value 0000 - 1111 S5L9291X digital signal processor 36 $9e command (default values d [7:0] = 0000 0000) digital clv control command address data d7 d6 d5 d4 d3 d2 d1 d0 clv control 5 10011110 ($9e) soffset[7:0] soffset[7:0]: smds offset output the final error which add the soffset in smds error when splus is "1" $9f command (default values d[7:0]:=0000 0000) control of function modes in dsp command address data d7 d6 d5 d4 d3 d2 d1 d0 clv control 6 10011111 ($9f) - - - - - - - clv dfct clv_dfct if efm pulse width is greater than 64t, the signal is indicates defect and smdp and smds outputs are set to hi-z so, it (ed: what does "it" refer to?) does not control clv. h : defect detection control , l : normal control digital signal processor S5L9291X 37 $a0 command (default values d[7:0]:=0000 0000) 10band eq. filter gain control command address data d7 d6 d5 d4 d3 d2 d1 d0 10band eq. filter gain control 1 10100000 ($a0) - filter gain level(31hz) [ed: cannot understand what these sentences are saying.] $a1 command (default values d[7:0]:=0000 0000) 10band eq. filter gain control command address data d7 d6 d5 d4 d3 d2 d1 d0 10band eq. filter gain control 2 10100001 ($a1) - filter gain level(62hz) [4:0] is the level of gain which is multiplied by band1. $a2 command (default values d[7:0]:=0000 0000) 10band eq. filter gain control command address data d7 d6 d5 d4 d3 d2 d1 d0 10band eq. filter gain control 3 10100010 ($a2) - filter gain level(125hz) [4:0] it is the level of gain that multiplied by band2. S5L9291X digital signal processor 38 $a3 command (default values d[7:0]:=0000 0000) 10band eq. filter gain control command address data d7 d6 d5 d4 d3 d2 d1 d0 10band eq. filter gain control 4 10100011 ($a3) - filter gain level(250hz) [4:0] is the level of gain which is multiplied by band3. $a4 command (default values d[7:0]:=0000 0000) 10band eq. filter gain control command address data d7 d6 d5 d4 d3 d2 d1 d0 10band eq. filter gain control 5 10100100 ($a4) - filter gain level(500hz) [4:0] is the level of gain which is multiplied by band4. $a5 command (default values d[7:0]:=0000 0000) 10band eq. filter gain control command address data d7 d6 d5 d4 d3 d2 d1 d0 10band eq. filter gain control 6 10100101 ($a5) - filter gain level(1khz) [4:0] is the level of gain which is multiplied by band5. $a6 command (default values d[7:0]:=0000 0000) 10band eq. filter gain control command address data d7 d6 d5 d4 d3 d2 d1 d0 10band eq. filter gain control 7 10100110 ($a6) - filter gain level (2khz) [4:0] is the level of gain which is multiplied by band 6. digital signal processor S5L9291X 39 $a7 command (default values d[7:0]:=0000 0000) 10band eq. filter gain control command address data d7 d6 d5 d4 d3 d2 d1 d0 10band eq. filter gain control 8 10100111 ($a7) - filter gain level (4khz) [4:0] is the level of gain which is multiplied by band 7. $a8 command (default values d[7:0]:=0000 0000) 10band eq. filter gain control command address data d7 d6 d5 d4 d3 d2 d1 d0 10band eq. filter gain control 9 10101000 ($a8) - filter gain level (8khz) [4:0] is the level of gain which is multiplied by band 8. $a9 command ( default values d [7:0] = 0000 0000 ) 10band eq. filter gain control command address data d7 d6 d5 d4 d3 d2 d1 d0 10band eq. filter gain control 10 10101001 ($a9) - filter gain level (16khz) [4:0] is the level of gain which is multiplied by band 9. S5L9291X digital signal processor 40 $aa command (default values d[7:0] = 1000 0000) volume gain control command address data d7 d6 d5 d4 d3 d2 d1 d0 volume gain control 10101010 ($aa) eqrst eqon volon volume gain control d[7] : band equalizer reset l : reset enable h : reset disable d[6] : band equalizer on/off h : on l : off d[5] : digital volume only mode on/off h : on (no band equalization) l : off d[4:0] volume gain must be input from 0 to 31.the actual gain value is inside the ic, and the micom controls the volume level according to the proper input value. digital signal processor S5L9291X 41 $ae command (default values d[7:0]:=0000 0000) 1-bit dac mode control command address data d7 d6 d5 d4 d3 d2 d1 d0 1-bit dac control 10101110 ($ae) - - - - sc[1:0] sf[1:0] sf[1:0] 1-bit dac & datx sampling frequency control in the control status data, it controls the sampling rate(bit24 ? bit27) from digital audio output signal(datx) sf[1:0] audio sampling frequency 00 44.1 khz 01 48 khz 11 32 khz others reserved sc[1:0] calibration range scale control bits name data=00 data=01 data=10 data=11 comment d[1:0] sc[1:0] x1 x2 x4 x0.5 zero detection mute used available S5L9291X digital signal processor 42 $af command (default values d[7:0] = 0000 0000) output signal on/off control and monitor output signal selection command address data d7 d6 d5 d4 d3 d2 d1 d0 output port control 1 10101111 ($af) - talk[2:0] mnt hiz - rfck oen sbdt dumb talk[2:0] monitoring terminal output selection bit name output description talk[2:0] mnt5 mnt4 mnt3 mnt2 mnt1 mnt0 000 0 0 0 0 0 0 001 fsync efmflag ecfl3 ecfl2 ecfl1 ecfl0 010 fsync fsdw ulkfs emph sqok tim2 011 dac_sadt dac_lrck dac_bck esp_bck esp_lrck esp_sadt 100 fchange divn98 divnfast at2t efmin efmout 101 divn1[5] divn1[4] divn1[3] divn1[2] divn1[1] divn1[0] 110 dac_sadt dac_lrck dac_bck dsp_bck dsp_lrck dsp_sadt 111 flag6 shock status ovfl empty dcomp match signal name esp off(x1 ? x2) esp on(x1 ? x2) comment dac_lrck, dac_bck, dac_sadt x1 ? x2 x1 dsp output, dac input dsp_lrck, dsp_bck, dsp_sadt x1 ? x2 x1 ? x2 dsp output esp_lrck, esp_bck, esp_sadt - x1 esp output mnt_hiz h : mnt[2:0] hi-z output (input mode) l : mnt[2:0] normal output rfck_oen h : rfck output, l : rfck input sbdt dumb h : output off, l : output on digital signal processor S5L9291X 43 $b0 command ( default values d [7:0] = 0000 0000 ) esp memory system setting command address data d7 d6 d5 d4 d3 d2 d1 d0 ms control 10110000 ($b0) mswre n mswac l msrde n msrac l msdcn 2 msdcn 1 waqv mson mswren: memory system write enable (adpcm encoding on/off) h: write enable l: write disable mswacl: memory system write address clear h: clear enable l: clear disable msrden: memory system read enable (adpcm decoding on/off) h: read enable l: read disable msracl: memory system read address clear h: clear enable l: clear disable msdcn2, msdcn1: memory system data compare/connection control msdcn2 msdcn1 mode 0 0 connection operation disable 0 1 direct connection 1 0 2-pair connection 1 1 3-pair connection waqv: q data valid h: valid l: invalid mson: memory system on/off (esp on/off) h: on l: off S5L9291X digital signal processor 44 $b1 command ( default values d [7:0] = 0000 0000 ) command address data d7 d6 d5 d4 d3 d2 d1 d0 data control 1 10110001 ($b1) - yflgs yfckp cmp12 - comp [1:0] yflgs, yfck jitb signal input conditional control yflgs yfclk mode 0 0 rfck input negative edge, jitb = 'l' 0 1 rfck input positive edge, jitb = 'l' 1 0 jitb = 'l' 1 1 jitb = 'h' cmp12: 12/16 bits comparison connection h: 12-bit comparison connection l: 16-bit comparison connection comp[1:0] encoded data comparison mode control comp [1:0] mode 0 0 4-bit comparison 0 1 5-bit comparison 1 0 6-bit comparison 1 1 full bits comparison digital signal processor S5L9291X 45 $b2 command (default values d[7:0] = 0000 0000) command address data d7 d6 d5 d4 d3 d2 d1 d0 data control 2 10110010 ($b2) bbw wff mcp esp reset jitb off shock en shock sw cmd shock bbw blkck(s0s1) blocking signal from waqv. h : blocking l : no blocking . wff waqv forced falling signal within a particular region. h : no forced falling. l : forced falling. mcp repeat sound mis-connection protect. h : protect. l : no protect. esp reset esp block reset while at 'h'. h : all esp block reset. l : normal jitb_off jitb signal is not used for shock processing. h : jitb signal not used. l : jitb signal used. shock_en determines whether the external input shock sense signal (sbck) and micom command shock sense signal(cmd_shock) should be used at shock processing h : use shock sense signal (use sbck lead when using external signal) l : not use shock sense signal. shock_sw determines whether to use the shock sense signal should be used as an external lead or as an internal micom command. h : use as external lead(sbck) l : use as internal micom command(cmd_shock) cmd_shock internal shock sense signal h : shock generation l : shock not generated S5L9291X digital signal processor 46 $b3 command (default values d[7:0] = 0000 0000) command address data d7 d6 d5 d4 d3 d2 d1 d0 data control 3 10110011 ($b3) sbc en - - sbc[4:0] sbc en: sqok bad count setting enable blkck(s0s1) blocking signal from waqv. h : enable l : not enable. sbc: sqok bad count setting value := sbc * 2 shock $b4 command (default values d[7:0] = 1000 0000) command address data d7 d6 d5 d4 d3 d2 d1 d0 data control 4 10110100 ($b4) dram ctrl ram type ram bank ram_bus[1:0] ram_size[2:0] dramctrl dram ctrl on/off control h : dram ctrl on l : dram ctrl off ram[6:0] ram_type ram_bank ram_bus[1:0] ram_size[2:0] 0 : edo dram 0 : 2 bank ?? 00 : x4 ? 000 : 4m ? 1 : sdram 1 : 4 bank ?? 01 : x8 001 : 16m 10 : x16 010 : 32m(16m 2ea) ?? 11 : x16(reserved) 011 : 64m 100 : 128m 101 : 128m(64m 2ea) 110 : 256m 111 : 256m(128m 2ea) 1) sdram only, 2) edo dram only 2 bank in the sdram is consist in only 16m and 64m. digital signal processor S5L9291X 47 $b5 command (default values d [7:0] = 0000 0000) command address data s7 s6 s5 s4 s3 s2 s1 s0 m7-m0 ms state 1 10110101 ($b5) flag6 msovfl dcomp mswi h msrih - flag6: jitb signal, reset after $b5h status read. h: jitter margin overflow msovfl: memory system overflow pulse, reset after $b5h status read. h: write overflow dcomp: data compare/connection operation h: compare/connection operating now mswih: encoding sequence stop due to internal states h: encoding stop msrih: decoding sequence stop due to internal states, reset after $b5h status read. h: decoding stop $b6 command (default values d [7:0] = 0000 0000) command address data s7 s6 s5 s4 s3 s2 s1 s0 m7-m0 ms state 2 10110110 ($b6) msemp ovfl encod decod - msemp: valid data empty state h: invalid (when ra exceed vwa) l: valid ovfl: write overflow state h: memory full encod: encoding sequence operating state h: encoding now decod: decoding sequence operating state h: decoding now S5L9291X digital signal processor 48 $b7 command memory system valid data residual command address data ms data residual 10110111($b7) r[15:0] r[15:0] := valid data accumulated vwa-ra anti-shock memory valid data residual bit function x4 x8 x16 r15 64m bits 128m bits r14 32m bits 64m bits 128m bits r13 16m bits 32m bits 64m bits r12 8m bits 16m bits 32m bits r11 4m bits 8m bits 16m bits r10 2m bits 4m bits 8m bits r9 1m bits 2m bits 4m bits r8 512k bits 1m bits 2m bits r7 256k bits 512k bits 1m bits r6 128k bits 256k bits 512k bits r5 64k bits 128k bits 256k bits r4 32k bits 64k bits 128k bits r3 16k bits 32k bits 64k bits r2 8k bits 16k bits 32k bits r1 4k bits 8k bits 16k bits r0 4k bits 8k bits digital signal processor S5L9291X 49 $ba ? $bd command write data from micom to external dram command address data istat d7 d6 d5 d4 d3 d2 d1 d0 terminal dram access 0 10111010 ($ba) mwr mrd - - mad(11:8) hi-z dram access 1 10111011 ($bb) mad [7:0] hi-z dram access 2 10111100 ($bc) wrdata [15:8] hi-z dram access 3 10111101 ($bd) wrdata [7:0] hi-z mwr sign bit for writing the datum of wrdata[15:0] to dram mad[11:0] address h : write enable reset after writing to dram mrd storing in rdrdata[15:0] after datum reading from dram mad[11:0] address h : read enable reset after writing to dram mad[11:0] dram read/write address wrdata[15:0] dram write data S5L9291X digital signal processor 50 bf command write data from external dram to micom command address data d[15:0] dram access read data 1011_1111 ($bf) rddata[15:0] rddata[15:0] dram read data digital signal processor S5L9291X 51 $f0 command ( default values d [7:0] = 0000 0000 ) data processing speed control command address data d7 d6 d5 d4 d3 d2 d1 d0 play mode control 11110000 ($f0) ds1 ds0 - - play sw dfck play[1:0] ds1, ds0 x1, x2 speed control ds1 ds0 mode 0 0 1x 1 1 2x play_sw normal play mode change by external test pin or micom command this function can be enabled only when test[3] pin is ?l?. l : test pin control h : micom command control dfck 1-bit dac speed control h : 2x, l : 1x play1, play0 normal play mode bit name test pin mode comment play[1:0] test[3:0] 0 0 0 0 0 0 normal 1 serial audio data interface impossible 0 1 0 0 0 1 normal 2 serial audio data interface impossible, (3-band eq is off) 1 0 0 0 1 0 normal 3 serial audio data interface possible (audio out block data output) 1 1 0 0 1 1 normal 4 serial audio data interface possible (esp block data ) S5L9291X digital signal processor 52 efm demodulation emf block is a circuit, which demodulates the emf signal read from the disc, and is composed of the frame sync detection circuit and the control signal generator circuit. efm demodulation when the modulated 14 channel bit data is input, they are demodulated to 8 bit data. the demodulated data are classified into two types, the subcode data and audio data. the subcode data is input to the subcode processing block and the audio data is stored in the internal sram, after which it is corrected for error. frame sync detection/protection/insertion frame sync detection the data is configured in the unit of frames, of which frame sync, subcode data, audio data, redundancy data are configured in one frame. the frame sync is detected because it is used as the reference signal to synchronize the data output from the frame sync for extracting correct data. (related command register: $92, fsmd [1:0]) frame sync protection/insertion frame sync may be detected in data besides that of frame sync or omitted due to effects from disc defects or jitters etc. in such cases, frame sync must be protected and inserted. a window must be made according to the $92 command register?s wsel[1:0] to protect frame sync. the data that enter this frame syn is the valid data and the frame sync that exits this window is ignored. if frame sync is not detected in the frame sync protection window, the frame sync made in the internal counter is inserted. if frame sync is inserted continuously to reach the number of frames specified by fsel[1:0] of the $92 command register, the frame sync protection window is ignored as ulkfs becomes ?h? and the following frame sync detected is immediately accepted. if the frame sync is accepted, ulkfs signal becomes ?l? to accept the frame sync detected in the window. digital signal processor S5L9291X 53 subcode the subcode sync signal sos1 is detected in the subcode sync block. after so is detected, s1 is detected after one frame passes. at this time, so+s1 signal is output through the sos1 terminal, and sos1 signal is output through the sbdt terminal when the sos1 signal is ? h?. of the data input to the efmi terminal, 14-bit subcode data is efm demodulated, synchronized with the wfck signal to become 8-bit (p, q, r, s, t, u, v, w) subcode data and output as sbdt through the sbck clock. of the 8 subcode data, only q data is selected and saved in 80 shift registers using the wfck signal. the crc results of the stored data are synchronized to the s0s1 positive edge and output through the sqok. if the crc results are error, ?l? is output to the sqok terminal and, if not, ?h? is output. if crcq?s $93 command register is ?h?, crc results are output through the sqdt terminal from the interval that sos1 is ?h? to the negative edge of sqck. the following illustrates the timing diagram of the subcode block. sqck, sqdt, s0s1 timing relationship sqok(n) q4 q3 q2 q1 q8 q7 q6 q5 q80 q79 q78 q77 q4 q3 sqok(n+1) 0 q4 q3 q2 q1 q8 q7 q6 q5 q80 q79 q78 q77 q4 q3 0 sos1 sqok sqck sqdt (crcq=1) sqdt (crcq=0) ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ note: if crcq of the subcode-q data is ?h?, sqok signal is output through sqdt according to the sqck signal and, if crcq is ?l?, sqok signal is not output through sqdt. sbdt, sbck timing relationship i 1 2 3 4 5 6 7 8 q r s t u v w iii ii wfck sbck sbdt i) sbck is set to ?l? for approximately 10us after wfck becomes negative edge. ii) if sos1 is ?l?, subcode p is output but , if sos1 is ?h?, sos1 is output. iii) if more than 7 pulses are input to the sbck terminal, subcode data p, q, r, s, t, u, v, w data are output repeatedly. (notice) value of $b2 address bck pin xxxx_x11x external shock perception signal (atsc) with it is used value of others both sbdt and sbck are used. S5L9291X digital signal processor 54 cd text if texton is ?l? at $95 command register, subcode data are provided through sbck and sbdt , but if ?h?, sbck and sbdt cannot be used. if textout is ?l? at $95 command resister, q datum is provided through sbck,sqdt, but if ?l?, text data, instead of qdatum, are output. text data are output one bit at a time through the sqdt at the falling edge of sqck. first, crc 4bit datum, in which each pack(16bit) may have or not have an error, is output, and then the real text data are output from msb to lsb. for example, if the first bit of crc is ?h?, it means that the first pack has no error. sqck,sqdt,s0s1 timing relationship crc3 sqok q data crc 0 pack1 pack2 pack3 pack4 sqok crc1 crc2 crc4 0 r1 s1 t1 u1 v1 w1 r2 s2 t2 u2 v2 w2 r3 s3 t3 u3 v3 w3 crc data id1(pack1) msb lsb id2(pack1) msb lsb s0s1 sqdt sqck textout sqdt sqck textout 80 clocks 520 clocks 4bits 4bits 16bytes 16bytes 16bytes 16bytes 0 0 0 digital signal processor S5L9291X 55 ecc (error correction code) if the data on the disc is damaged, the ecc (error correction code) block is used to correct data. the circ (cross interleaved reed-solomon code) is used to correct to 2 errors for c1 (32, 28) and 4 erasures for c2 (28, 24). for error correction, the data is processed in 1 symbol of 8-bit. furthermore, the ecc block has the pointer function which generates the c1 pointer for c1 correction and c2 pointer for c2 correction. c1 and c2 pointers output flags for ecc processed data to indicate that the data has error. this flag signal is input to the interpolation block and used to process the error data. the error correction results can be monitored through mnt3-mnto terminals. (related command register: $a9, talk[2:0]) mode mnt3 mnt2 mnt1 mnt0 comment ecfl3 ecfl2 ecfl1 ecfl0 c10 error 0 0 0 0 c1 flag = reset c11 error 0 0 1 0 c1 flag = reset c12 error 0 1 0 0 c1 flag = set/reset c1 correction impossible 1 0 0 0 c1 flag = set c20 error 0 0 0 1 c2 flag = reset c21 error 0 0 1 1 c2 flag = reset c22 error 0 1 0 1 c2 flag = reset c23 error 0 1 1 1 c2 flag = reset c24 error 1 0 0 c2 flag = reset c2 correction impossible 1 1 0 1 1 c2 flag = set c2 correction impossible 2 1 1 0 1 copy c1 flag interpolation when a burst error is generated on the disc, there are cases when the data cannot be corrected even with the ecc process. the interpolator block uses the ecc?s c2 pointer to interpolate the data. the audio data is input for l/r- ch in 8-bit c2 point, lower data 8-bit, and upper data 8-bit order, respectively, to the data bus. if c2po terminal is ?h? and there is only one error, the average value is interpolated, but, if there are 3 continuous errors, all values are hold interpolated. if lrck is ?l? for one lrck cycle, r- ch data is output, and, if ?h?, l- ch is output. the timing clock in the interpolator block is shown below. a b c d e f g h i j c2 pointer b: average value interpolation f = e = d: all value hold interpolation g: average value interpolation S5L9291X digital signal processor 56 serial audio data interface converts the 16-bit parallel data sent by the interpolation block to serial data. S5L9291X supports the following serial audio data format. the lrck frequency for 1x is 44.1khz and 2x is 88.3khz. 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 r-ch (msb) 15 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 l-ch (msb) 15 48 1 fs = 44.1/88.2khz 2 1 24 25 lrcho bcko sadto mute & attenuation the mute signal can be accepted in two ways. when mute port (pin #: 44) is ?h? when $91 command register?s d7 bit is ?h? the audio data is either muted or reduced based on the mute signal and attn signal of the $91 command register. zero cross mute after zcmt of the $91 command register is set to ?h?, and the mute signal becomes ?h?, and the audio data top 6- bit all are either ?l? or ?h?, the audio data is muted. mute when zcmt of $91 command register is ?l? and the mute signal becomes ?h?, the audio data is muted. attenuation the signal is reduced by the attn of $91 command register and mute signals. attn mute degree of attenuation [ db] 0 0 0 0 1 - 1 0 -12 1 1 -12 digital attenuation by referencing command register $5d, 2 6 = 64 attenuation levels can be controlled. when the reset signal becomes ?l?, the attenuation level is initialized to 0db. gain = 20 log dattn 64 digital signal processor S5L9291X 57 soft mute when the digital attenuation level is controlled from 0db to - db, the soft mute function can be configured. dac mute when the $91 command register?s dac_mute is ?h?, only the dac block is muted. digital audio out this digital audio out block outputs 2-channel and 16-bit data to another digital set in serial format based on the digital audio interface format. the advantage of this interface method is that communication is possible with only one pin, that is, additions such as a separate clock are not required. cd digital audio interface format x channel 1 y channel 2 z channel 1 y channel 2 x channel 1 y channel 2 subframe 1 subframe 2 frame 191 frame 0 frame 1 start of block 1) 1 block = 192 frame 2) 1 frame = 2 subframe 3) frame 0, channel 1 - block sync preamble, z included ch.1 format 4) frame 1, channel 1-frame 191, channel 1 ? ch.1 sync preamble, x included ch.1 format 5) frame 0, channel 2-frame 191, channel 2 ? ch.2 sync preamble, y included ch.2 format preamble aux p c u v audio data lsb msb 31 30 29 28 27 0 3 4 7 8 preamble aux data audio data valid data user data channel data parity data each subframe is composed of 32 time slots, and audio data is included in the subframe. two subframes make one frame, which has both left and right stereo signal components; 192 frames make one block, which is in the control bit data unit. S5L9291X digital signal processor 58 digital audio interface timing chart ... bit n bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit24 bit25 bit26 bit27 bit28 bit29 bit30 bit31 preamble z fs = 44.1khz 128fs digital audio out source coding channel coding (biphase mark) digital signal processor S5L9291X 59 subframe format preamble (4 bits): the preamble has each subframe and block sync data. the preamble is not converted to biphase signal to maintain the inherent characteristic of the sync. on the other hand, it starts with the values opposite the phase 1 values of all the. the preamble requires three patterns, that is, a pattern to distinguish between and right and patterns that indicate start of the block. these patterns are shown. preceding state 0 1 channel coding ?x? 11100010 00011101 subframe 1 ?y? 11100100 00011011 subframe 2 ?z? 11101000 00010111 subframe 1 and block start preamble ?x? is the channel 1 sync; preamble ?y? is the channel 2 sync; and preamble 3 is to show the start sync of the block. the reason that there are 2 sync patterns for preamble is that the value reverses according to the phase of the previous data. aux (4 bits): auxiliary data area. audio data (20 bits): although the audio data resolution for the cd transmitted to digital out is usually 16 bits, it can also be transmitted as 20 bits or 24 when aux is to be included. this area is lsb first. validity bit (1 bit): if the audio sample word can be converted to analog audio signal, the validity bit to ?1? and, if not, to ?0?. for the cd, set it to ?0?. user data (1 bit): this domain is used to transmit the subcode data for cd. control status data (1 bit): data is input for each subframe, and 192 subframes must be gathered to make one control data. this domain has both the consumer mode and professional mode, of which S5L9291X the consumer mode. the control status data for cd has the following meaning. parity data (1 bit): use even parity S5L9291X digital signal processor 60 bit control status data 0 0: consumer use, 1: professional use 1 0: normal audio, 1: non audio mode 2 0: copy prohibit, 1: copy permit 3 0: no pre-emphasis, 1: pre-emphasis 4 reserved = 0) 5 0: 2 channel, 1: 4 channel 6 ? 7 00: mode 0, reserved 8 ? 15 10000000: 2 channel cd player user bit channel = cd subcode v bit optional 16 ? 19 source number ( = 0000) 20 ? 23 channel number ( = 0000) 24 ? 27 sampling frequency: 44.1khz = 0000 28 ? 29 clock accuracy 00: normal accuracy 10: high accuracy 01: variable speed 30 ? 191 don?t care (all zero) digital signal processor S5L9291X 61 sigma-delta stereo dac as a digital-to-analog converter that uses the ? d modulation, the dac installed in S5L9291X is composed of the digital attenuation, de-emphasis filter, fir filter, sinc filter, digital sigma-delta modulator, analog post-filter, anti- image filter etc. normal input/output characteristics exist at 20khz. it has snr (signal to noise ratio) above 90db. timing chart 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 r-ch (msb) 15 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 l-ch (msb) 15 48 1 fs = 32/44.1/48khz 2 1 24 25 lrchi bcki sadti 32/44.1/48khz sampling frequency (fs) support (external master clock support) if the dac master clock is applied to the rfck terminal (pin#: 53) in 384 fs cycle, it supports 3 sampling frequencies. if the command register $94?s mscksw is ?h? and command register $a9?s rfck_oen is ?l?, the external master clock can be applied to the rfck terminal. x1, x2 speed support if the command register $93?s dfck is set to ?h?, the internal data input rate becomes 2*fs and the speed becomes 2x. application circuit 40 lchout 41 vdda_dac 42 vhalf 43 vref 44 vaas_dac 45 rchout 46 vddd_dac 47 vssd_dac 1uf 100k 0.1uf 10uf 0.1uf 10uf 0.1uf 10uf 1uf 100k 0.1uf 10uf lch rch S5L9291X digital signal processor 62 10-band eq. filter it has a digital filter inside the chip for equalizing the signal. it is possible to control eq gain using command resister $a0 ? $a2,a5 and three band eq digital filter features are as follows. audio input audio output pre-scaler limiter g1 : bass gain, g2 : mid gain, g3 : high gain 3band eq. block diagram 0 - 200hz 200hz - 8khz 8khz - 18khz g1 g2 g3 3band eq. frequency response digital signal processor S5L9291X 63 3band eq. bass frequency response 3band eq. mid. band frequency response S5L9291X digital signal processor 64 3band eq. high band frequency response micom command flow to drive the 3band eq., first the gains of each band must be set and the values must be converted to 16 (hex). examples of this is as follows: pre scale : 0db, bass : 10db, mid : -3db, high : -3db pre scale gain = 10 (0/20) = 1 ( dec) = 001.00000 (bin) = 20 (hex) bass gain = 10 (10/20) = 3.162277 ( dec) = 011.00101 (bin) = 65 (hex) mid gain = 10 (-3/20) = 0.707945 ( dec) = 000.10110 (bin) = 16 (hex) high gain = 10 (-3/20) = 0.707945 ( dec) = 000.10110 (bin) = 16 (hex) after calculating the pre-scale gain and different gains of each band, micom command is input in the order as shown in the flow chart below. digital signal processor S5L9291X 65 eq.start pre scale gain $a520 bass gain $a065 mid gain $a116 high gain $a216 soft mute on $5adfe wait 23.2ms 3 band eq. on $a440 soft mute off $5d00 eq.end soft mute on $5dfe wait 23.2ms 3 band eq. off $a400 soft mute off $5d00 normal (default) +3db +6db +10db -3db -6db -10db pre-scale $a520 $a52d $a53f $a565 $a516 $a510 $a50a bass $a020 $a02d $a03f $a065 $a016 $a010 $a00a mid $a120 $a12d $a13f $a165 $a116 $a110 $a10a high $a220 $a22d $a23f $a265 $a216 $a210 $a20a S5L9291X digital signal processor 66 digital clv servo this block controls the spindle motor speed by using rfck and wfck data to generate the control. digital clv servo control related command registers are $93, $94, and $98 ? $9e. forward (kick) mode mode ($99) that rotates the spindle motor in forward direction. smdp smds smef smon h hi-z l h reverse (brake) mode mode ($99) that rotates the spindle motor in the reverse direction. smdp smds smef smon l hi-z l h stop mode mode ($99) that stops the spindle motor. smdp smds smef smon l hi-z l l speed (clv-s) mode ($99) controls the spindle motor during a track jump or if the efm phase is unlocked. although the pulse width of the frame sync signal detected from the efm signal is exactly 22t in plck cycle (t), it can be greater or less than 22t depending on the player status. wb and wp of the command register $98 are used to control the frame sync detection cycle. smdp smds smef smon l : deceleration h : acceleration hi-z : remain hi-z l h detected frame sync pulse width smdp comment 21t = 22t 3 23t l (deceleration) hi-z (remain) h (acceleration) if the command register $98?s gain is ?l?, the smdp output is output after it has been attenuated by -12db, but if ?h?, it is output without being attenuated. digital signal processor S5L9291X 67 p22t n22t smdp deceleration acceleration = 22 t over 22 t under 22 t S5L9291X digital signal processor 68 xphsp (clv-a) mode (command register : $99) in this normal operation mode, the speed mode and phase mode are change alternately by the lock signal. after the lkfs signal generated by the frame sync block is sampled in wfck/16 cycles and is detected to be ?h?, the phase mode executes and, if it is detected as ?l? eight consecutive times, the speed mode automatically executes. high speed (clv-h) mode (command register : $99) in jump mode, in which servo has to traverse about 20,00 track roughly, servo moves from inner track of disc to outer. in that case, mirror signals about 20khz are overlapped in efm. so servo is to be unstable in speed-mode, because false mirror peak level , which is larger than frame sync, is detected. in high speed mode, peak hold uses 8.4672mhz/256 cycle and bottom hold uses rfck/16 or rfck/32 cycle, so it make possible to eliminate the mirror signals and for servo to be stable lock generation if the lkfs signal remains at ?l? for the frame time, provided by micom command $99?s unlock[1:0], or for less, lock remains at ?h?. however, if it remains at ?l? for more than the given frame, the lock changes to ?l?. the time in lock is the same for 1x and 2x speed. additional functions ($9b?s pos must be set to = ?h?) 1) smds masking this function prevents sensitive clv servo response to small frequency error changes. if the sme of $9a is set to ?h?, it operates in the smds masking mode (dead zone enable). the sml[1:0] masking range of $9b is set, and, if $9a?s smm bit is ?h?, sml value becomes the absolute value of the masking range, set by 9d?h smoffset[3:0], but if ?l?, then the value is set to the one shown in the table below. if smds frequency error, that is, wfck high width is within the masking range, the smds output is pwm of 50:50 or hi-z is output. (determined by $9a?s strio) if smds masking occurs, smdp output is masked automatically and hi-z is output. command order : $9b(sml) ? $9d(smoffset) ? $9a (sme, smm) sml[1:0] masking error range (sml = ?l?) 00 0 % 01 6.25 % 10 12.5 % 11 25 % < sml[1:0] setting > digital signal processor S5L9291X 69 masking error area (deas zone area) smds high width (t) 288t 288t maximum error area wfck wfck high width (t) 1t = 1/8.4672mhz < dead zone area > S5L9291X digital signal processor 70 smdp masking when the smds masking is enabled, the smdp output is automatically masked in the dead zone area. there are two modes for masking only the smdp without masking the smds. in the first mode, if $9a?s sme is set to ?l? and pme is set to ?h?, the smdp masking mode operates. at this time, if the phase error is greater than 50% or 25% of the wfck frequency error (determined by $9b?s pml), smdp output is masked. that is, the output is hi-z. this is to reduce the phase error effect at the state in which the frequency error is not sufficiently small. in the second mode, after setting sme and pme of $9a, pcen of $99 can be used to set smdp masking. in this case, if pcen of $99 is set to ?h? and wfck frequency error enters the dead zone area set by sml, the smdp output is maked to hi-z. command order : $9b(pml) ? $9a(pme), $9b(sml) ? $99(pcen) clv emergency mode (eclv) when there are events such as a focus drop, an unstable efm is input and this in turn causes the spindle motor to overload. to prevent such an overload, the micom notifies the clv servo of such emergency conditions, and then clv servo outputs h, hi-z and l repeatedly in regular intervals. this is all executed by the micom, which sets the eclv of $93 to ?h? and changes the clv mode to clv-s mode. then, smds outputs hi-z and smdp outputs h, hi-z and l repeatedly in an interval determined by eclv_pd of $93. eclv_pd comment 1 bottom hold pulse interval 0 peak hold pulse interval command order : $93(eclv, eclv_pd) ? $99(cm3,cm2,cm1,cm0) defect response mode if the efm enters as ?l? for a specific time due to a scratch or defect, there is no pll control, which fixes the plck to any frequency; this in turn fixes the wfck and consequently the clv servo output is fixed in the direction of acceleration or deceleration. in such a case, the final clv speed can be reduced when normal efm re-enters. if clv_dfct of $a2 is set to ?h?, the clv servo outputs, smdp and smds, can be output as hi-z and 50:50, when efm width is greater than 64t to prevent deceleration or acceleration. over sampling output the smds output frequency is 7.35khz at 1x speed and 14.7khz at 2x speed. these are within the audio frequency range, so they be used as normal audio output noise source. therefore, ovspl of $98 can be set to ?h? and smds and smdp frequencies can be over sampled by four times at 7.35khz * 4 = 29.4khz and output. if ovsplmd of $98 is set to ?h?, the smds becomes tri-state t output and, if set to ?l?, smds become a pwm output. clv idle mode this mode rotates the spindle motor at a fixed rate regardless of the efm input. to operate in the clv idle mode, the $9e?s soffset[7:0] value, which represents the smds high width, must be set. furthermore, if $99?s clv_idle is set to ?h?, the smdp output becomes hi-z, and smds outputs high for the duration of soffset set value * 118ns in one cycle and outputs hi-z in the remaining intervals. digital signal processor S5L9291X 71 smds soffset hi-z < smds output > smds gain control if the pickup or spindle motor is changed, the entire clv loop transfer function changes and thus clv gain must be controlled. the clv servo is changed to pi controller type; we can assume that the frequency error output smds controls the p gain and the phase error output smdp controls the i gain. smds gain can be set to 9b?h sgain[2:0] , where gain values of sgain are shown below. in terms of a graph, the gain is the slope. sgain[2:0] gain value rise_mtval 000 1 0 001 2 144 010 4 216 011 8 252 100 16 270 101 32 279 110 64 283 111 128 285 < smds gain setting > wfck high width (t) 1t = 1/8.4672mhz maximum error area rise_mtval smds high width (t) 288t 288t < smds gain vs smds output > S5L9291X digital signal processor 72 there is an additional feature which allows the addition of an offset to wfck frequency error for output. if $9d?s splus is set to ?h? and $9e?s soffset[7:0] is set, the soffset value is added to the frequency error, and the product of this value and the gain is output to smds. smdp gain control the 9b?h pos must be set to ?h? for smdp gain control. furthermore, smdp gain must be set to $9a?s pgain[1:0]. the clock resolution, which measures wfck and rfck?s phase error, must be set to $9a?s pksel. pgain[1:0] gain 00 1 01 1/2 10 1/4 11 2 digital signal processor S5L9291X 73 digital pll the existing digital pll (dpll) is used to enter the wide capture range pll mode, which allows the frequency of the frequency synthesizer, which supplies the dpll clock, to follow the bit rate change of the efm signal. once in the wide capture range pll mode, the jitter-free mode can be set to suppress the sram jitter that may be generated by the change in the input/output rate of the internal sram buffer. furthermore, multi-speed clv mode in 16 levels from 1x to 2x is possible. cntvol2 xinm vco1on dpdo1 xin efmi maxt<8:0> wfck vco1o m1 ref<1:0> wide m1 dpdo2 plck8m pll2ref xout jitfree xin plck xout16m p2 m2 pll1 pll2 to efm demodulation to ecc & interpolation or clv s2 1/p1 1/m1 loop filter1 vco1 1/s1 cntvol1 maxt count dpll divm determine mux 1/p2 phase detector1 phase detector2 loop filter2 1/m2 vco2 1/s2 < block diagram > S5L9291X digital signal processor 74 pll1, a frequency synthesizer which supplies dpll reference clock, uses the input (16.9344mhz) from the crystal to generate a clock of frequency that is a multiple of plck frequency. pll2 is a frequency synthesizer which supports the entire speed range clv or jitter-free mode. therefore, pll2 is set to the power down mode when it is not used in normal 1x and 2x mode or jitter free1 mode. in the entire speed range clv mode, the output frequency of pll2 the crystal input to be used as either the clv mode reference clock and data operation(ecc, interpolation) reference clock; in the jitter free2 mode, the output together with the dpll plck8m input is used as data operation reference clock. the entire speed range clv mode and jitterfree2 mode cannot be set simultaneously. the equation of the output frequency from the frequency synthesizer is as follows. divider value changes with mode. fout fin m p s = fin: input frequency, fout: output frequency p: pre-divider(=divp+2), m: main-divider(divm+8), s: post- scalor(2 divs) in the entire speed range clv mode , once the values for divs1 and divp1 of 8a address are set according to speed, the remaining divider values are automatically set. commands according to speed are as follows. command speed 8a f0 0.5 6e 00 ? ? 1 56 00 1.04 55 1.09 54 1.14 53 1.2 52 1.26 51 1.33 50 1.41 4f 1.5 1e f4 1.55 1d 1.6 1c 1.66 1b 1.71 1a 1.78 19 1.85 18 1.92 17 2 16 ? ? digital signal processor S5L9291X 75 electrical shock proof (esp) the esp(electrical shock proof) block has the data compression/restoration functions, recovery decompression/restoration functions for anti-shock proofing of compact disc players and dram memory control function. the compression ratio is about 4/16bit, 5/16, and 6/16 and shock proof data storage memory sizes are 4m /4mx2/16m dram. feature 1) 2-channel processing 2) serial data input : 2?s complement, 16-bit/msb first 3) anti-shock memory controller 4) ars(anti-rolling system) support : x1 ? x4 compression possible 5) compression method n 4-bit compression mode 2.91s/mbit n 5-bit compression mode 2.34s/mbit n 6-bit compression mode 1.95s/mbit n full-bit non-compression mode 0.743s/mbit 6) 3 internal dram configurations selectable n 4m dram (1mx4 bits) n 8m dram (1mx4 bits 2ea) n 16m dram (4mx4 bits) 7) microcontroller interface n serial command write and internal state read-out n data residual quantity detector : 16-bit output no compression lrcki bcki sadti (88.2khz) lrcko bcko sadto (44.1khz) no compression external dram 1. 4m 2. 4mx2 3. 16m we data[3:0] addr[11:0] ras cas oe gnd spc encoder dram i/f psc decoder < esp block diagram > S5L9291X digital signal processor 76 anti-shock operation the shock-proof mode uses the data storage dram. if the micom command $b0?s mson = ?h?, shock-proof operation executes. encode sequence in the encode sequence, the audio data from the cd data processor (cdp) is encoded through the esp encoder and the compressed data is stored in the data storage dram. encode sequence internal stop if there is an data storage dram buffer overflow or shock(jitb==?l? or cmd_shock==?h?), esp is stopped internally regardless of the micom command $b0?s mswren. the encoding starts when there is a match by compare-connect sequence or a direct-connect command input. decode sequence the esp decoder checks the system stability in the micom and the presence of the data which can be sent to the dram. if they both check out to be normal, the micom command $b0?s msrden is set to ?h? and decoding starts. before the decoder starts, the mute/attenuation function for data output control is put on normal. data compare-connect sequence ? encoding stops when it detects a cdp system shock or dram overflow. ? once the system shock stabilizes or the dram data is less than the amount specified in the micom pgm and the micom command $b0?s msdcn1(or = msdcn2) = mswren = ?h?, it executes the data compare- connect start command. ? if the data compare-connect matches normally or direct - connect command is input, the data compare - connect processing comes to an end and encoding begins. the audio data input at this time is directly connected to the last valid data. dram refresh method ? the 16 cycle?s ras only refresh begins at the mson rising edge. dram address 1) to address the basically supported 4m/8m(4m+4m)/16m dram, the address register size is 22 bit and the dram is accessed in the form of a circular buffer. 2) ra : the data address read from the dram for decoding is stored. as long as it is not ?empty?, the read operation continues. ?empty? state occurs when ra and vwa becomes the same. 3) wa : the dram address to which the encoded data is stored. if compare-connect is operating or ? ovfl (overflow)? condition exists, this also stops along with the encoding. when compare-connect sequence begins, the data written after vwa becomes meaningless and writing must begin again starting from the address directed by vwa. 4) vwa : updated to the current wa value by the micom?s waqv. 5) as shown in the following figure < wa / ra mapping> , ra becomes the address of the first data to be decoded and wa becomes the address value following the last encoded data. therefore, as wa increases and the writing ends and it becomes the same value as ra, dram overflows and the encoding stops. digital signal processor S5L9291X 77 ra wa encoded data wa ra vwa vwa x2 x1 x1 x2 S5L9291X digital signal processor 78 $b1 address initial setting dram selection 4m dram 8m dram 16m dram flag6 setting selection jitb in falling edge of rfck jitb in rising edge of rfcl jitb l jitb h 12/16-bit compare selection 12-bit compare 16-bit compare compression mode selection 4-bit mode 5-bit mode 6-bit mode full-bit mode $b1,00xx_xxxx $b1,01xx_xxxx $b1,1xxx_xxxx $b1,xx00_xxxx $b1,xx01_xxxx $b1,xx10_xxxx $b1,xx11_xxxx $b1,xxxx_1xxx $b1,xxxx_0xxx $b1,xxxx_xx00 $b1,xxxx_xx01 $b1,xxxx_xx10 $b1,xxxx_xx11 digital signal processor S5L9291X 79 key operation sequence key operation yes no yes (skip/stop/ pause/search key) yes no no no yes no yes yes no key operation sequence esp on/off toggle key? soft attn on (fadeout) sequence waiting fade out completed(23.2ms) esp on ? esp reset sequence through mode sequence esp on ? play key? esp start sequence special key? soft attn on (fadeout) sequence waiting fade out completed(23.2ms) esp reset sequence skip key? stop key? pause key? stop go next music esp start sequence pause key sequence search key sequence no yes no yes end through mode sequence means a normal 1x play. in pause key sequence , play/skip/stop key must be entered one more time. S5L9291X digital signal processor 80 pause key sequence yes yes no yes no no pause key sequence waiting key input play key? esp start sequence skip key? go next music stop key? stop digital signal processor S5L9291X 81 search key sequence yes no search key sequence x1 fast search ??????? search key off? esp start sequence 1-bit dac mute off $91,0000_0000 S5L9291X digital signal processor 82 esp start sequence yes no esp start sequence 1-bit dac mute off $91,0000_0000 s0s1 falling edge & sqok esp encode/decode sequence encode command $b0,10000001 digital signal processor S5L9291X 83 esp encode/decode sequence yes no yes no 0 0 1 no yes 0 1 yes no yes no yes no esp encode/decode sequence esp status read ($b5,$b6) subq read crc check waqv command $b0,10100011 memory residual read ($b6) cmd_shock enable $b2,0000_0101 $b2,0000_0100 wait minimum 0.9ms fok error 100ms track back jump & compare routine soft attn on sequence esp reset sequence compare command $b0,1010_1101 esp status read ($b5) passes the position to be connected? s0s1 falling edge flag6? encod/ shock? msemp? sqok? 4-block crc-bad? msemp? dcomp? S5L9291X digital signal processor 84 soft attn on sequence in soft attn command, fade_in or fade_out functions can be operated within 23.2ms fade out :when $5d,1111_1110 command is entered, sound is fade out within 23.2ms fade in: when $5d,1111_1110 command is entered, that is , from the start position of the music in fade out, when $5d 0000_0010 command is entered, sound is fade in within 23.2ms. soft attn on sequence yes no yes no yes no soft attn on sequence soft attn on $5d,0000_0010 fade out ? soft attn on $5d,1111_1110 fade out within 23.3ms fade in fade out state? forbidden soft attn on $5d,0000_0010 fade in within 23.2ms attenuation level setting $5d,xxxx_xx10 digital signal processor S5L9291X 85 esp time display sequence yes no yes no yes no esp time display sequence s0s1 falling edge q=subq read q and qdisplay same music memory residual read ($b6) qstored=valid data size qdisplay=q-qstored qlast=last q of last music1 if( time of music2< dram size) qlast2=last q of last music2 wait the increment timer count up qdisplay=qdisplay+1 qdisplay > qlast S5L9291X digital signal processor 86 esp time display figure qlast q qstored qdisplay music1 music2 time cd reading position hearing(displaying) position esp datx sequence in normal x1 speed mode, esp on, or external mp3 mode, for obtaining the datx output. $91,0000_0001 command is used. digital signal processor S5L9291X 87 package dimension 100-tqfp-1414 #100 14.00 16.00 0.20 14.00 16.00 0.20 0.08 max 0.127 + 0.073 - 0.037 0-7 note : dimensions are in millimeters. #1 0.50 (1.00) 0.45-0.75 0.05-0.15 1.00 0.05 1.20 max 0.20 + 0.07 - 0.03 S5L9291X digital signal processor 88 notes |
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